Thin polished plates such as silicon wafers and the like are a very important part of modern technology. A wafer, for instance, may refer to a thin slice of semiconductor material used in the fabrication of integrated circuits and other devices. Other examples of thin polished plates may include magnetic disc substrates, gauge blocks and the like. While the technique described here refers mainly to wafers, it is to be understood that the technique also is applicable to other types of polished plates as well. The term wafer and the term thin polished plate may be used interchangeably in the present disclosure.
Fabricating semiconductor devices typically includes processing a substrate such as a semiconductor wafer using a number of semiconductor fabrication processes. For example, lithography is a semiconductor fabrication process that involves transferring a pattern from a reticle to a resist arranged on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etching, deposition, and ion implantation.
Generally, certain requirements are established for the flatness and thickness uniformity of the wafers. However, the various process steps performed during fabrication may alter stresses in the thin films deposited on the wafers and result in elastic deformation that can cause significant distortions, including in-plane distortions (IPD) and/or out-plane distortions (OPD). Such distortions may lead to errors in downstream processes. For example, distortions may lead to overlay errors in lithographic patterning or the like.
Asymmetric overlay error signatures have also been observed during semiconductor fabrication. Asymmetricity in this case is defined as signatures that deviate from rotational symmetry. For example an overlay signature is said to be fully symmetric or axisymmetric if the overlay error varies along the radius of the wafer but at a given radial location the value of overlay error is the same irrespective of the angular location on the wafer. Components of overlay error signature that deviate from axisymmetry are said to be asymmetric components/signatures. It is noted that a majority of these asymmetric signatures tend to be non-correctable by traditional and advanced lithography scanner-based overlay correction strategies. These asymmetric signatures may be induced by various process tools such as film deposition, thermal annealing and the like. Therein lies a need for systems and methods to help address potential issues that may be caused by such asymmetric signatures.